WHAT'S NEXT, IN THE ACTUAL ORDER

Building a real STARK-based VM with unconstrained branching, memory, and a full RISC-V-compatible instruction set is a multi-year effort for a team, not a single session. This project picked the smallest slice that still has the essential hard part: an AIR whose transition constraints correctly gate multiple instruction types via opcode selectors, with per-row assertions that bind the proof to an exact program — the same core technique (generalized) that real STARK-based VMs like RISC Zero, SP1, Cairo, and Miden use. Once that pattern is validated, extending it is additive work, not a redesign.

1. Loops: a dynamically-sized trace (bounded by a max-cycle count, padded/truncated based on actual execution length) so JZ/JNZ can jump backward too. The "verifier re-executes and asserts everything" trick still works — but trace-length selection and the resulting proof-size variability need real design.
2. Addressable memory (dynamic addresses, distinct from the static register file) — worth checking first whether the same re-execute-and-assert trick extends here before assuming a full permutation/lookup argument is required.
3. Only after 1–2 are solid: consider RV32I compatibility.